IBM unveils new architecture to develop 5nm fingernail-sized chip

IBM unveils new architecture to develop 5nm fingernail-sized chip
IBM has unveiled plans to create a new 5nm chip as it moves away from the FinFET architecture to a new structure built with a stack of four nanosheets.

Moore’s law, coined first in 1970, is the observation that the number of transistors that can be accommodated on a single chip doubles almost every two years. The trend has held up more or less and the latest data point supporting the law has just emerged. The smallest chips currently available are made up of transistors that are 10nm long. 

But the new structure allows some 30 billion transistors to be packed onto a chip the size of a fingernail and promises significant gains in power and efficiency. 

Semiconductors have been made using the FinFET architecture since about 2011. These transistors are fin-shaped, with three current-carrying channels surrounded by an insulating layer. The IBM team believes shrinking the fins any further won't do much to improve their performance.

The 5nm chips are made using stacked silicon nanosheets, which can send signals through four gates at once, instead of FinFET's three. They're created using Extreme Ultraviolet (EUV) lithography, a process that writes patterns on a silicon wafer using a much higher energy wavelength of light than the current technique.

Compared to the current 10 nm chips, the 5 nm prototypes are capable of improving performance by 40 percent at fixed power, or provide a power saving of 75 percent at matched performance. The development could lead to smaller, more powerful and more efficient devices – but with 10 nm chips only just hitting the market, and 7 nm due for commercial release in 2019, these 5 nm chips are probably still about four years away.

Source: IBM